Silicon observatory / No. 004

Inside the ARM1.

A 32-bit processor in 25,000 transistors. Look at everything they left out.

1985INTRODUCED

32 bitDATA WIDTH

≈6 MHzCLOCK

25,000TRANSISTORS

02 / Framebuffer

This page's own invention

BASE&100000

SIZE320×200

PIXEL3:3:2 RGB

TIMERoff

The ARM1 had no display hardware at all — it was a prototype on a board that plugged into a BBC Micro. This framebuffer and the timer are invented here so the demos have somewhere to draw. One byte per pixel, three bits of red, three of green, two of blue, no palette and no interleaving.

03 / Processor die

Acorn ARM1

INSTRUCTION&00000000

PC&0000000

EXECUTED0

SKIPPED0

Ready. Step to fetch and execute the first instruction.

04 / Registers

Banked registers in orange

R15 is the program counter and the status register in one word: flags at the top, mode at the bottom, and 24 bits of word address in between. Reading it gives this instruction's address plus 8, because two more are already in the pipeline.

05 / Memory

&008000

Thirty-two words at a time, little-endian, one row per eight. Green outline marks the program counter. Words changed by the last instruction flash.

Execution trace

Newest first · last 60

No instructions executed.

06 / Disassembly

Click a line to toggle a breakpoint. Highlight = next instruction. Every instruction carries its condition in the top four bits, so the suffix is part of the mnemonic.

Assembly workbench

Edit source, then assemble & reset

Ready.

Assembly quick reference

Numbers: &100000 hex, %1010 binary, 42 decimal, 'A' character. . alone is the current address. Every mnemonic takes a condition suffix and most take S to set the flags: ADDS, BLNE, MOVEQ, SUBNES.

MOV R0, #1
MVN R0, #0
ADDS R1, R2, R3
ADD R1, R2, R3, LSL #4
ADD R1, R2, R3, LSR R4
MOV R0, R1, RRX
CMP R0, #10
TST R0, #&80
B label / BL routine
MOV PC, LRLDR R0, [R1]
LDR R0, [R1, #4]!
STRB R0, [R1], #1
LDR R0, [R1, R2, LSL #2]
LDR R0, =&12345678
STMFD SP!, {R0-R3, LR}
LDMFD SP!, {R0-R3, PC}
SWI #0

ORG · EQU · DCB · DCW
DCD · FILL · ALIGN · POOL

An ARM immediate is an 8-bit value rotated right by an even number of places. Most 32-bit constants cannot be written as one, so use LDR R0, =value and the assembler puts the word in a literal pool for you. POOL places that pool; otherwise it goes at the end.

A label named DONE gets a debugger breakpoint automatically.

Model & limitations

This is ARMv1, which is what the 1985 silicon ran: sixteen data-processing operations, B and BL, LDR and STR, LDM and STM, and SWI. That is the entire instruction set. There is no MUL — multiply arrived with ARM2 — no SWP, no coprocessor instructions, no MRS or MSR, and no MMU, because on an Archimedes that was a separate chip called MEMC.

Every instruction is conditional and every operand 2 goes through the barrel shifter, including the LSR #0, ASR #0 and RRX forms and the shifter's carry-out. R15 holds the flags, the interrupt disables, a 24-bit word program counter and the mode, all in one register. Reading it gives the instruction's address plus 8, or plus 12 for the shifted register when the shift amount comes from another register; storing it gives plus 12. Those are pipeline artefacts and they are modelled.

Memory is 1 MB of RAM from zero. An address beyond 26 bits raises a real address exception through the vector at &14, which is genuine ARM1 behaviour that disappeared after ARM2. Prefetch and data aborts are never raised, because nothing here can abort a transfer.

The framebuffer at &100000 and the timer at &200000 are this page's inventions, not Acorn hardware. The ARM1 had no display of its own; it lived on an evaluation board plugged into a BBC Micro, and it was the ARM2 that reached the Archimedes. Nothing else answers: unmapped reads return zero.

Instruction-level emulation. The clock advances by a count of memory cycles per instruction, which is how the ARM datasheets describe timing, but no bus contention or memory speed is modelled. No firmware sets anything up, so this page does: R13 starts at &10000 for user and supervisor, &F000 for IRQ and &E000 for FIQ so the banks do not share a stack, the mode is SVC, and execution begins at the first ORG rather than at the reset vector.

Keyboard: Space run/pause, S step, B back, R reset. Shortcuts are inactive inside controls. Back undoes up to 512 instructions.

Inside the ARM1.

02 / Framebuffer

03 / Processor die

04 / Registers

05 / Memory

Execution trace

07 / The instruction set

08 / What it got right, and what it got wrong

What it got right

What it got wrong