Inside RISC I.
The Berkeley chip that named RISC. Thirty-one instructions, one cycle each — and most of the silicon spent on registers that slide over one another on every procedure call.
02 / Pipeline & data path
Two stages · delayed jump03 / Register windows
Each wedge is one window's LOW and LOCAL registers; a window's HIGH registers are the next wedge's LOW. CALL turns the ring one wedge clockwise (CWP−1), RET turns it back. SWP marks the window kept free for the oldest frame's HIGH registers: a CALL into it traps, and the handler spills the oldest frame to memory.
06 / Disassembly
Assembly workbench
Assembly quick reference
Berkeley order: sources first, destination last. # marks an immediate, which must fit in 13 bits (−4096…4095). Append ,{c} to an ALU instruction to set the condition codes. Numbers: 42, 0x2A, &2A, '*'; . is the current address.
sub r1,r2,r3,{c}
sll r1,#4,r2
ldl (r3)8,r4
ldbs (r3)r5,r6
stl r4,(r3)8
ldhi #&6F56E,r1
jmpr ne,loop
jmp alw,(r2)0
callr fn,ra
ret (ra)8getpsw r1 · putpsw r1
gtlpc r1 · callint r1
retint (loc1)0
nop · mov r1,r2
cmp r1,#0
set #0xDEADBEEF,r1
halt
.word .half .byte .space
.align .ascii .asciz
NAME = expr
Conditions: gt le ge lt hi los lo his pl mi ne eq nv v alw nev (also gtu lequ ltu gequ). lo is the PDP-11 borrow: unsigned less-than after a subtract.
Register names that follow the window, so one program runs on both register files: in0… (HIGH: arguments in, results out), loc0… (LOCAL), out0… (LOW: arguments to a callee), and ra = r31. Gold has 4 in, 6 loc, 4 out; the architecture 6, 10, 6. Call with callr fn,ra and return with ret (ra)8: CALL leaves its own address in the callee's ra, and +8 skips the call and its delay slot. osp and gpsw belong to the trap handlers — leave them alone.
Programs start at &4000. (r0)offset reaches only the bottom and top 4 KB of the address space; use set to put a label's address in a register.
Model & limitations
From the papers: the 31 instructions of Table 2 and their operand forms; the formats of Table 3; r0 hard-wired to zero; the delayed jump; one cycle per instruction and two for loads and stores; the PDP-11 condition set; and both register files — the architecture's 138 registers in 8 windows of 22 overlapping by 6 with 10 globals, and the Gold chip's 78 in 6 windows of 14 overlapping by 4 with 18 globals (p.13). Gold's split into 4 HIGH, 6 LOCAL and 4 LOW follows from those numbers.
This page's reconstructions, because none of the three papers gives them: the opcode numbers; the encoding of the sixteen conditions; the PSW layout (N Z V C, SWP, CWP, I, PI); the trap mechanism and its vectors at &10, &18 and &20; the window-spill handlers and their register conventions; little-endian byte order and the alignment check; the memory map; and exactly when CALL and RET change the window. Table 2's "next" is ambiguous. Here the window changes with the CALL or RET itself, so a CALL's delay slot runs in the callee's window and a RET's in the caller's — the reading that lets a trap return with jmp and ret as a pair.
As on the chip, registers are not mapped into memory — the papers describe the idea, but "this scheme has not actually been implemented in the first versions of the RISC I & RISC II chips" (p.6). The assembler refuses {c} on loads and shifts, which is how Berkeley worked around the chip's one design error (p.16). Setting that bit anyway stops the page, since what the flawed silicon did is not recorded.
Timing counts cycles: one per instruction, two for a load or store, one for trap entry. Memory never waits. The readouts turn cycles into time at the 2 µs the real chips achieved and the 400 ns the designers planned for.
The terminal is invented. Interrupt handlers run in the window below with interrupts off; they must not CALL, because a window overflow inside one would spill into a live frame.
Keyboard: Space run/pause, S step, B back, R reset. Back undoes up to 1,000 manual steps; running clears that history.