Inside the T414.
A processor built to be one of many. The scheduler is in the microcode, a channel is a word of memory, and four serial links make the wiring between chips part of the language.
02 / The network
03 / Link analyser
04 / Processor 0
idle08 / Compiled code
Workbench
occam quick reference
Operators: + - * / \ (checked), PLUS MINUS TIMES (wrap round), /\ \/ >< << >> ~, = <> < > <= >= AFTER, AND OR NOT. This page accepts ordinary precedence; real occam insists on brackets. >> is a logical shift — the T414 has no other.
Networks: CONNECT 0:1 TO 1:0 wires processor 0's link 1 to processor 1's link 0, then each PROCESSOR n holds that chip's program, indented. Processor 0's link 0 always goes to the host. Link channels are link0.out … link3.in.
Assembly: Inmos mnemonics, one instruction per line, label:, .byte, .word. j, cj and call take a label; the assembler builds the pfix/nfix sequences.
Model & limitations
From Inmos: every T414 instruction the page implements follows the register predicates of the Compiler Writer's Guide, appendix F, with the cycle counts of the T414's own engineering data. The scheduler (two priority queues through (Wptr−2), timeslicing every 1024 µs, high priority interrupting low through the save area at #8000002C), the timers (1 µs and 64 µs clocks, sorted timer lists), channel words, the ALT states in (Wptr−3) to (Wptr−5), the memory map (2 KB on chip, MemStart #80000048), the link packets and the boot protocol are all as documented. The link timing reproduces the databook's 400 KB/s one way and 800 KB/s both ways.
Not modelled: roundsn and postnormsn, whose informal specification is too loose to reproduce bit for bit (the page stops with a message); testhardchan and the register-test instructions; the Event pin; Analyse; external memory wait states — all 64 KB here runs at on-chip speed; and the 58-cycle worst case of interrupt latency (the typical 19 cycles are charged). Undefined register values are whatever the instruction left.
This page's own: the occam compiler (a subset, with the Guide's translations, except that every PAR branch gets its own workspace and procedures get a static link); the startup code that empties the queues and starts the clocks, which on a real system is the boot program's job; loading programs straight into memory (only the assembly demo uses the boot protocol, because a boot packet is at most 255 bytes); the CONNECT and PROCESSOR syntax; the host; the 64 KB of memory; and the link's internal turnaround delay, chosen to hit the databook's throughput.
Keyboard: Space run/pause, S step, B back, R reset. Back undoes up to 400 manual steps; running clears that history.