Silicon observatory / No. 001

Inside the 4004.

A small machine. A very big beginning. Watch every instruction happen.

1971INTRODUCED

4 bitDATA WIDTH

740 kHzCLOCK

2,300TRANSISTORS

02 / Processor die

Intel MCS-4

ACC · BINARY0000

PC · HEX000

INSTRUCTIONS0

CLOCK PERIODS0

Ready. Step to fetch and execute the first instruction.

03 / Register file

Changes glow green

Three return addresses · newest first · 0 active calls

04 / Data memory

Four 16-nibble registers per chip. Amber outlines the SRC-selected character. Status below follows the selected register.

Execution trace

Newest first · last 60

No instructions executed.

05 / ROM disassembly

Click a line to toggle a breakpoint. Highlight = next instruction. Step always executes once.

Assembly workbench

Edit source, then assemble & reset

Ready.

Assembly quick reference

Numbers are decimal, 0xFF hex, or 0b1010 binary. Registers: R0–R15. Pairs: P0–P7. Labels end in :. Use .ORG address and .BYTE value, value for ROM data. Semicolons begin source annotations.

FIM P0, 0x12
SRC P0
FIN P1
JIN P1
LD R0 / XCH R0
LDM 7
ADD R1 / SUB R1
INC R1
ISZ R1, labelJUN label
JMS label / BBL 0
JCN 4, label
WRM / RDM
WMP / WRR / RDR
WR0–WR3 / RD0–RD3
ADM / SBM
CLB CLC IAC CMC CMA
RAL RAR TCC DAC
TCS STC DAA KBP DCL

JCN condition bits: 1 = TEST low, 2 = carry set, 4 = A zero. Combine with OR; bit 8 inverts the result. Local branches must address the page of the PC after the instruction.

A label named DONE gets a debugger breakpoint automatically. There is no HALT instruction. Infinite loops are normal.

Model & limitations

Instruction-level emulation, not a transistor or bus-phase simulation. Instructions cost 8 or 16 clock periods; FIN is one byte but takes 16. Diagram highlights are conceptual data flow, not physical chip layout.

4 KB ROM, sixteen 4-bit registers, accumulator, carry, TEST input, and a four-slot circular PC/return stack. RAM uses an explicitly modeled external 3-to-8 bank decoder: DCL values 0–7 select independent banks, each with four 4002 chips. Physical CM-RAM line combinations are not simulated.

Separate input/output latches model sixteen ROM ports; the switches drive input port 0. WPM is recognized but pauses with an error: a writable-program-memory interface is not installed. No original Busicom ROM is included; all demos are small original 4004 programs.

Keyboard: Space run/pause, S step, B back, R reset. Shortcuts are inactive inside controls. Back restores up to 256 instruction snapshots, including input state.

Inside the 4004.

02 / Processor die

03 / Register file

04 / Data memory

Execution trace

06 / The instruction set

07 / What it got right, and what it got wrong

What it got right

What it got wrong